A.Matrosova, T. Bohan

Tomsk State University, Russia

The main problem in sef-testing with random patterns in verification of the test quality, i.e., the computation of the test fault coverage. The number of random inputs applied during testing is closely related to an affordable test time and can by very large. Application of a random test patterns which is far from being exhaustive requires its quality verification . Unfortunately simulation of long random patterns against logic structures does not seem practical. Consequently , we had to seek for an analytical solution.

The random testing quality problem can be spelled out as follows. For a given combinational circuit that has to be tested with N random patterns one should find single stuck faults detected with a probability less than P if they exist. P is the given threshold. A similar problem has been discussed in the paper [1]. Its authors have proposed to replace a detection probability with a signal probability and then obtain signal probability bounds instead of the precise value. In the paper [2] a precise method of a signal probability calculation is suggested . If a signal probability of a fault is less than P one should obtain its detection probability.

A precise method of a detection probability calculation is suggested in this paper. It is based on using orthogonal disjunctive forms (ODNFs). A disjunctive form is orthogonal if its any two conjunctions are orthogonal w.r.t., a certain variable, i.e. one of them contains this variable without an inversion, and the other has this variable with an inversion. The proved theorems allow cutting the calculation required. A computer tool is developed to estimate possibilities of the method through using bench-marks and other practical circuits.

If the detection probability of the stuck faults is less than P the fault is called a "hard fault". Having increased the number of random patterns one can try to make this fault an "casy" one. If the necessary increase is impossible the fault remains a "hard" one and cannot be detected. In this case one should modify the logic to make the fault easy detected. The developed tool allows to verify a testability of combinational circuit that is find its "bad" nodes if they exist.

  1. Savir J., Ditlow G.S., Bardell P.H. Random Pattern Testability. IEEE on computer VC-33, N 1, 1984

  2. Yevtushenko N.V. and Matrosova A. U. Random Approach to logical Circuit Nodes Controllability and Observability. Avtomatika I Telemehanika, 1993, N 11, pp 152-156 (in Russian)