This paper outlines the development of technology independent reusable, parameterized telecommunication based switching and routing macro-block and evaluate their performance.Today's VLSI design and production technology has improved up to a level where integration of complete systems on chips containing millions of transistors in a reality. As the complexity increases, needs for new design methods are obvious to manage large and complex design. The main objectives are to shorten the design cycle, to preserve the technology independence, and to avoid technology obsolescence.
Structural design methodology is the necessities for time-to-market VLSI circuits. Such a methodology must be based on an extensive use of libraries of generic components and reusable macro-blocks. Reusability depends on design methodology and standardization of CAD environments, macro-function interfaces, and technology porta bility. The macro-library is the boundary block between IC design and system design.
The availability of a Macro-library allows directly to implement sub-behaviours at the functional level. Even a small macro block may consists of adders, shifters, multiplexers, registers memories, comparators, and selectors. The building blocks(BBs) in these libraries are parameterized so that they can be reused under many different circumstances by assigning actual values to formal parameters for word length, load conditions, terminal positions, and so on. The mapping of operations on to hardware operators and the expansion functions for complex operations are described in MACRO libraries.
To verify the functional correctness we used logic simulation, and synthesis. Design specification and implementation architecture described in high level language (VHDL) and then simulated with actual values for the inputs. Synthesis is used for pattern matching to reconstruct the hierarchical structure of the design to the gate level. The reconstructed structure can then be compared with original structure using a netlist comparison tools. Synthesis checks the consistency of two structural descriptions at different expansion levels. Models can be used in ASICs as functional units of a large design or as stand-alone components along with external processor.
Macro-library provides technology independent block, reduced area while meeting comparable timing requirement. easy to optimize, better performance of the critical paths of the synthesized circuits, and save cost of creating and maintaining of library. Application specific macro function models using VHDL, allowing more time to the designer for specifying the system and making technology independent architectural selections.
The main goal of this work was to develop and model using VHDL, static and programmable switches with parallel architectures. Typical models are "Coprin switch" and "knockout Switch" units and so on. Coprin switch operates with links at 280 Mbits/s, cells of 15 bytes information and 1 byte header and consisted of a 16x16 square basic switching element, used data, voice, and video sources of communication. The switch consists of multiplexer, buffer memory, demultiplexer, and control parts. All cells are treated as a parallel stream of information, and cells are handled sequentially by a central control entity. Knockout switch operates at 155Mbits/s, based on the output queuing solution. Switching principle is identical for small and large values of the number of inlets and outlets. Fixed length cells arrive on each inlet in a regular time frame, and each operating at an equal speed.
ATM switch requires very high speeds with a global bit rate of several Gbits/s, provide very small delay (less than 1 ms), and must have low cell loss rate. This is only possible using hardware switching fabric which are made up of small cell-routing units called switching components (macro-blocks), that may be organized into multi-level structure. Finally, we shortly discuss the application, uses, and benefit of Telecom-macro-library in telecommunication system.