Department of Electrical Engineering
Michigan State University
East Lansing, MI 48824
International Solomon University, Kiev, Ukraine
The described method was implemented in the program ANALYZER. The ANALYZER was implemented in C language on a SUN 3/50 workstation running Unix 4.2BSD. We tested the ANALYZER using ten random generated systems and circuits, two benchmarks: Primary 1 and Primary 2, and several example circuits. Experimental results of the length prediction for these examples are represented. The estimations of ANALYZER are quite comparable to the best real results.
The experimental investigation of the ANALYZER for nMOS integrated circuits and bipolar integrated circuits on the base of the master slice has shown that in many cases its results are quite lose to the manual design. Comparison our predictions with manual designs is also summarized.
The new T1, T2-Rules, provided a basis for direct estimation of the interconnection length which is not possible with Rent's Rule. Numerous experiments have been done to secure comparative data: theoretical results versus empirical data. We learned that: