|Axel Jantsch||(Siemens AG, Austria )||firstname.lastname@example.org|
AKKA takes a C/C++ specification as input to the system, this code is then compiled with a modified GNU C compiler. After compilations and execution of the specification, the tools extract the following information: software execution time, object access count, hardware estimations (cost and hardware execution time) and parameters describing the architecture. This information is used in the hardware-software partitioning process, which can be fully automatic or user guided. If the partition is made user guided, it is done with in a graph browsing tool, daVinci. It present the system in a graphical way together with analysis results. The user can choice implementation style by marking functions and loops to either hardware and software.
Behavioral VHDL code is generated for hardware parts and system bus interfaces. For the software parts, the code generation replaces the code intended for hardware with interfaces to the hardware. The behavioral VHDL code is synthesized with the high level synthesis tool SYNT. AKKA provide a co-verification mechanism for the hardware and software, this is done with help of UNIX sockets. Co-verification can be performed before and after synthesis, with out any changes on either the hardware or software interfaces.
With in the tool set, there is support for co-emulation and prototyping. For the hardware parts we target a Xilinx based reconfigurable board, from Virtual Computer Inc., which have a X4013 device on it. This board is situated in a Sparc IPX workstation, connected with the SBus. The software parts is also implemented on the workstation.