Workbench for Design Improvement

E. Fehlauer, K. Feske, G. Franke, M. Koegst, H.-G. Martin, St. Rülke

FhG IIS Erlangen - Department EAS Dresden Zeunerstr. 38, 01069 Dresden, Germany email: ruelke@eas.iis.fhg.de

Motivation:

The product development of digital circuits requires in many cases design cycles. Reasons for that may be things like incremental changes in the product specification after having started the design process or the violation of design constraints in the result of particular design steps (clock cycle, throughput, area, power con sumption, ...). However, the aim of design improvement is to avoid redesigns or to reduce the number of design cycles such that an initially synthesized circuit, which is functionally correct but does not fit certain design con straints, will be optimized as good as necessary by minor local changes at the level of the synthesized structure. Depending on the specific requirements of the design task, the circuit characteristics, and the violated design con straints different techniques are known gaining design improvement. Moreover, our working group has investi gated some effort to develop novel optimization techniques suitable for design improvement especially in the field of timing improvement of data paths by retiming, but also in other domains like controller optimization by FSM encoding techniques or high level approaches considering both, controller as well as data paths. The available variety of design improvement methods rises the problem that designers who want to optimize a design need an environment enabling the application of design improvement techniques in an easy way. Such an environment is our workbench.

Organization of the Full Paper:

Starting with an discussion of methodological aspects of our workbench we want to explain its main principles. Further, we will present design improvement methods integrated in the exper imental version of the workbench. Hereby we summarize the state of the art of such methods and present a selec tion of our novel techniques. As an example, our tool ECTP for pipeline retiming will be shown in greater detail. After having presented the components of the workbench, principles of their implementation, and their applica tion in the design process, we will conclude with experimental results and an outlook to future developments.

Main Principles of the Workbench:

Most of all, the workbench provides an environment supporting designers in utilizing optimization methods which are adapted to the peculiarity of the present design improvement prob lem. Further principles are the creation of alternative solutions by alternative approaches, the combination of dif ferent design improvement methods in a single process, and the capability to run experiments with different approaches or different parameters of a particular approach. This includes the composition of design flows (sequence of approaches) and the computer-aided evaluation of results obtained. Consequently, besides the aspects of methodology, suitable workbench kits (e.g. graphical front-end, analysis, definition of design flow sce narios, preprocessing of results, on-line help) as well as techniques enabling the easy integration of approaches for design improvement into the workbench are required. Our experimental version of the workbench solves these problems in an easy, practicable, and flexible manner.

Design Improvement Methods Incorporated in the Workbench:

In the present experimental version the work bench contains approaches aiming to different design domains (controller, datapath, both), different levels of abstractions (gate level, RT level, high level), and different optimization goals (timing in terms of clock cycles and throughput, area, power, multi-criterion optimization). Most of the tools incorporated are developments of our working group and carry out novel approaches like power driven state encoding, optimal pipeline retiming, or retiming including the controller. Particularly the tool ECTP for pipeline retiming provides good solutions, if the task is to fit a given clock cycle constraint by insertion of pipeline stages. ECTP generates the related registers optimally (minimal number of registers and pipeline stages) and combines iteratively pipelining with other opti mization methods (e.g. combinational area optimization). Controlled by parameters and basing on a modular con struction system of its tool architecture, ECTP can by adopted to different design conditions including the utilization of individual libraries.

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