Institute of Computer Systems
Slovak Academy of Sciences
Dúbravská cesta 9
842 37 Bratislava
The task of delay fault testing is to make sure that a logic circuit meets the timing specification and operates correctly at the desired clock rate. This paper presents a contribution to the delay fault investigation at the Register Transfer (RT) level. Our interest was focused into two directions - one was based on an analysis of the RT-statements with the goal to cover transitions into registers and the second on the perturbation of the Register Transfer Language (RTL) constructions. The main goal is to generate tests for these faults.
A delay of a register transfer between source registers and a destination register is modelled as a propagation time, when the values from source registers are transferred through a "black box" into the destination register. A path in the "black box" is assumed to have a delay fault, if the propagation time is greater than the clock interval which synchronises the transfer into registers. The delay faults produce delayed transitions, but the delayed transitions are filtered or changed in logic errors after the propagation through a register. This depends on the fault site and the fault delay of the propagation path with respect to the sample time provided by the clock signal.
The RTL distinguishes two types of the transfer: a pure transfer ( e.g. A <- IN1 ) and a non-pure transfer (e.g. C <- NOT A ). On this basis with the knowledge of the delay fault modelling at the gate level  two types of delay faults at the RT-level were proposed: a register transfer delay fault and an operation delay fault.
The investigation of dynamic effects at the RT-level was based on the REGGEN system - the ATPG system for a fault model based on faulty components of the RT-statement which generates a test set for static faults , and was divided into two directions: for an implicit cycle-based timing model and for an explicit timing model.
The first approach is an analysis of the RT-statements and their operators with the investigation of the fault delay propagation from a target RT-statement with results of test set for an individual RT-statement. A set of test patterns based on an analysis of RT-statements and different RT-operators was proposed for testing of the delay faults. A number of test patterns in the test set is independent on the length of registers. These test patterns - an initial pattern and test patterns to test an individual RT-statement for delay faults - are used for a fault activation phase. Based on a partition of the RT-description into functional submodules with a dependency on the timing model a justification procedure to the primary inputs and a fault propagation to the primary outputs are solved.
The second approach is based on the perturbation of the RTL construction - directly in the internal model of the RTL statements in a circuit description. It means the RTL syntax used in the REGGEN TPG system had to be modified to this time model. A declaration part was extended by the declaration of a time interval with the syntax: DELAY T: <integer number>, where <integer number> is a number of time units when a new value is transferred to the destination register. The other extension was done in the RT-statement by a time condition: k: (T ,c) Rd <- f (Rs1 , Rsi) , ->n where T means that the transfer from the source side is executed and a value in the destination register is available after a "default" time interval. All RT-statements executed after this RT-statement until a new time condition arrives are executed in the same time interval. The syntax was extended also by other keyword - after for another modelling in connection with the RT-statement k: (T ,c) Rd <- f (Rs1 , Rsi) after <integer number>, ->n. <integer number> specifies a time delay of the RT-operation. For this extended syntax a compiler from RTL description into the internal structure was implemented. Then the simulation system was modified to be able to execute the RT-statement according to the time conditions. The keyword after was used for an injection of the delay fault into the RT-statement. After the fault injection the order of the RT-statements is modified according to the time conditions and values in output registers received after the fault simulation are compared with values received after the fault-free simulation. Input data into simulator were prepared on the function of the RT-description. An example will be included in the full paper to show the proposed methodology.
This work was supported by the ESPRIT 6575 Project - ATSEC (Advanced Test Generation and Testable Design Methodology for Sequential Circuits).