Test Pattern Generation at the Behavioral Level from VHDL Circuit Description Containing Several Processes

The complex VLSI design with VHDL description requires Test Pattern Generation (TPG) techniques at different levels. TPG at the gate level can produce high quality tests, but they represent very expensive and time consuming problems for complex circuits. Therefore research in this area is focused on a higher level. The progress was oriented to the behavioral level based on VHDL modelling.

This paper presents TPG methodology at the behavioral level based on perturbation of VHDL construction. This methodology is proposed for VHDL subset and for VHDL circuit description modelled by several processes. VHDL circuit description can be represented by Process Model Graph (PMG) [1] and modelled as a data flow graph with the high primitives as nodes of the graph. Fault model is based on perturbation of VHDL construction and only a single fault will be investigated at a time. Based on the description of fault model the lists of faults for every node and for the whole VHDL system are created. This approach is focused to the eight types of faults (stuck-then and stuck-else faults, assignment control data, dead clause fault, dead process fault, dead statement, global stuck-data faults, local stuck-data faults, micro-operation faults). TPG algorithm and fault simulation technique work with propagation of G/B (Good/Bad) value pair and works in the interaction mode. TPG algorithm is solved by three basic steps:
- Control and data faults are used which perturb the operation of the language constructions in the model.
- Each of these perturbation (faults) are injected into the behavioral model.
- For each of the perturbation a test is found by propagating the effect of the faults to a primary output.

The presented TPG algorithm is based on an analogy with structural testing at the gate level on three main steps - fault activation, fault effect propagation and constraints justification. Received test for one fault is an input into the fault simulation process. The fault simulation process consists of three main steps, too [2]:
- Fault free simulation of a node using fault free input. The result is a fault free output.
- Sequential fault simulation for faults from a node.
- Propagation of fault list from the previous node.

This paper presents general steps and procedures of TPG methodology for three faults - micro-operation faults, assignment control faults and local stuck-data faults documented by a small example.

This work is supported by COPERNICUS CP93: 9624 FUTEG - Functional Test Generation and Diagnosis.

References

1. Armstrong, J.A., Gray, F.G.: Structured Logic Design with VHDL, A Simon & Schuster Company, Englewood Cliffs, NJ 07632, ISBN 0-13-885206-1, 1993.

2. Duda, M., Bezáková, J., Gramatová E.: Fault Simulation Algorithm on Behavioral Level from VHDL Description Containing Several Processes, Second Workshop on Hierarchical Test Generation, Duisburg, Germany, Sept. 1995, p.39.