M.Koegst, G.Franke, K.Feske
FhG IIS Erlangen - Department EAS Dresden
In the literature different approaches and synthesis meth ods are published [DeM-95]. At the logic level there are three main viewpoints for power minimization: factorization including restructuring [RoB-93], state assignment [BeM95] and logic minimization [SSL-92].
The goal of our paper is to present a new FSM state assignment procedure for low power and to demonstrate our strategy for low power design and power estimation with regard to user-specified input sequences.
In generalization of [RoP-93] we define for a given FSM the register switching rate d(C) for its state assignment C with regard to a given input sequence of the length N by
where are n(si,sj) the number of transitions between the states si and sj and H the Hamming distance of codes.
Our state assignment procedure consists of following steps:
Figure 1 Strategy for design and power estimation
Experimental results show the effectiveness of our state assignment procedure for reducing the power dissipation.
[DeM -95] Devadas,S.; Malik,S.: A Survey of Optimization Tech niques Targeting Low Power VLSI Circuits. 32th DAC, 1995, pp. 242-247.
[MDL-94] Monteiro,J.; Devadas,S., Lin,B.: A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. 31th DAC, 1994, pp. 12-17.
[MKD-94] Monteiro,J.; Kukula,J.; Devadas,S.; Neto,H.: Bitwise Encoding of Finite State Machines. International Confer ence on VLSI Design, Calcutta, India, January 1994, pp.379-382.
[RoP-93] Roy, K.; Prasad, S. C.: Circuit Activity Based Logic Synthesis for Low Power Reliable Operations. IEEE Trans act. on VLSI Systems, vol. 1, No.4, Dec. 1993.
[SSL-92] Sentovich,E.; et.al.: "SIS: A System for Sequential Circuit Synthesis", Memo UCB/ERL M92/41, University of Berkeley, CA, 1992