V. Spacek, J. Molnar, V. Stopjakova, B. Weber

In this paper a novel approach to Iddq testing is proposed. The method is based on sensing the Iddq current by means of a current conveyor and evaluating its value by a current comparator. The output is a pass/fail flag. In this approach no current to voltage conversion is needed. The circuit is designed to be implemented on a chip.

The circuit consists of an operational amplifier based second generation positive current conveyor CCII+ operating in class AB and a current comparator. The opamp is designed for high frequency and high slew rate. (10MHz, 100V/ms). The transmission ratio of the current conveyor is 0.1. It is a compromise between the transmission of high current peaks and low quiescent currents. The Built-In Current (BIC) monitor works with an external current reference.

Measuring the Iddq current off-chip causes difficulties for a testing hardware and significant decrease in the test rate. Therefore several techniques for Built-In current monitoring have been proposed. The main advantage of evaluating the Iddq current inside the chip is in bigger sensitivity to small defective currents as they can be masked by large leakage currents within pads.

Most of the BIC monitors that has been published so far use to convert the defective current to voltage by a sensing element (i.e. resistor, bipolar or CMOS transistor, etc.). This in most cases decreases in operational speed of the circuit. Exception is, of course, the Keating-Meyer principle, which takes a voltage drop from the parasitic capacitance of a device under the test.

In the paper there will be detailed description of the circuit functionality and simulation results presented.

Iddq Testing, Buil-In Current monitoring, Current Conveyor, Design for Testability