Test Synthesis from Register-Transfer Level Descriptions

Jaan Raik, Priidu Paomets

Electronics Competence Centre
Tallinn Technical University


Current paper presents a test synthesis system from register-transfer level (RTL) descriptions. The system includes test generators for datapath and control parts of the design and utilizes a logic-level synthesis tool. In the system, different design abstraction levels (RTL and gate-level) are described by alternative graph (AG) models. The uniform AG representation allows application of common formalism and procedures on these levels.

As the degree of integration in VLSI designs has been growing year-by-year, so has the need for automation of different design tasks. Design automation helps to shorten the time-to-market cycle and increases significantly designer's productivity. The automation was first introduced on the lower levels of design tasks, like placement and routing, and together with the growth of design complexities, moved gradually to higher levels, e.g. logic synthesis, high-level synthesis (HLS) and hardware/software co-design. Nowadays the goal is clearly to automate the entire design cycle from conceptualization to generation of silicon layout.

During recent years, more-and-more commercial and non-commercial high-level synthesis tools have become available. These tools are used by designers to automatically generate register-transfer level (RTL) descriptions from design's behavioral description. In the RTL descriptions the design has been partitioned into a control part, i.e. a finite state machine, and a datapath part containing a network of interconnected functional units (FU). Usually the HLS tools take into account several constraints, as speed, area, or testability, and allow the designer to quickly compare the trade-offs between alternative RTL implementations.

With the appearance of high-level synthesis a number of automated test generation approaches were developed which took advantage of register-transfer level information while generating tests for gate-level faults. Current paper presents an approach of test synthesis from RTL descriptions. The system is based on alternative graph (AG) models and contains test generators for datapath and control parts. The uniform AG model representation allows application of common procedures through different design abstraction levels. In the presented implementation these levels are register-transfer level (referred to as high level) and gate level (referred to as low level), respectively. The system utilizes Design Compiler from Synopsys Inc. for logic-level synthesis.

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