A Constraint-Driven Gate-Level Test Generator

In recent times, a lot of effort has been made in the field of functional testing to solve the problem of testing complex digital devices. However, the functional test generation approaches are often ineffective due to the lack of information about the structural implementation on higher model abstraction levels. At present, more and more digital circuits are being created through designer's interaction with high-level synthesis (HLS) tools. The output of these tools is register-transfer (RT) level description, i.e. representation where design has been partitioned into control (a finite state machine) and datapath (network of functional units) parts.

A hierarchical test generation method for gate-level datapath faults will be presented. The method operates on two design abstraction levels: RT-level (referred to as higher level) and gate level (lower level). Hierarchical test generation approach is based on the 'divide and conquer' principle. In the approach device under test is considered at different abstraction levels and test generation is performed on these levels by utilizing an appropriate test generation tool. In hierarchical testing, top-down and bottom-up strategies are known. In the bottom-up approach, tests generated at the lower abstraction level will later be assembled at the higher level. Current paper describes a hierarchical system implementing the top-down approach, where constraints extracted at higher level are taken into account while deriving tests for the lower level.