This paper describes a possible methodology to implement controlled built in self test (BIST) on digital integrated circuits. It makes use of existing design for test (DFT) methods and it also supports the use of different DFT methods in the same design. This implemented BIST methodology can easily be reused, at any time, during the designs entire life time. The test application time at the PCB or MCM level can be reduced if circuits used has both Boundary Scan (BS) and this BIST methodology implemented. Synthesis of the test strategy can be performed.
This work is supported by the Swedish National Board for Industrial and Technical Development (NUTEK)