Monday, October 4, 2004
Advanced topics of thermal testing of digital circuits

1. A. Poppe (Budapest University of Technology and Economics, Hungary)
   Measurement, modeling and simulation of thermal dynamics in microelectronic structures
2. M. Janicki (University of Lodz, Poland)
   Inverse Heat Conduction Problems in Microelectronics with Special Consideration of Analytical Thermal Analysis Methods

Tuesday, October 5, 2004
Advanced topics of SOC design and test

1. S. Kumar (Jönköping University, Sweden)
   Networks on Chip (NoC): a new paradigm for SoC Design (3h)
2. Z. Pliva (Technical University of Liberec, Czech Republic)
   BIST in SOC (2h)

Wednesday, October 6, 2004
Advanced topics of digital and analog test

1. W. Pleskacz (Warsaw University of Technology Poland)
   Defect Analysis and Probability Evaluation for Test Improvement (45 min)
2. V. Stopjakova (Slovak University of Technology)
   Current-based Test Methods for Digital and Mixed-signal Circuits (45 min)
3. E. Gramatova (Institute of Informatics of the Slovak Academy of Sciences)
   Test Generation for Delay Fault Testing (45 min)
4. S. Mosin (Vladimir State Technical University, Russia)
   Design-for-testability of analogue and mixed-signal circuits (45 min)
5. B. Magnhagen (Jönköping University, Sweden)
   Electrical test is not enough. (45 min)

Abstract

The following topics will be discussed during the lecture: thermal transient testing: (measurement methods and available tools, DCP measurements); evaluation of thermal transients (heating/cooling curves) by the NID method: time-constant spectra, structure functions, RC models derived from transient curves; structure functions as models of the physical structure (using structure functions for heat-flow path reconstruction and for creating compact models for thermal simulation purposes); creating compact models from thermal transient curves by optimization; using dynamic compact models in thermal and electro-thermal simulation.

Abstract

The following topics will be discussed during the lecture: fundamentals of heat transfer in solids (heat equation, solution methods, Green's functions), inverse heat conduction problems (problem definition, function and parameter estimation), methods of solving inverse problems (regularization and function specification methods), practical examples of inverse problems in electronics (material property estimation, power and temperature estimation). Additionally, a thermal FDM simulator publicly accessible directly from Internet will be presented.

Abstract

According to the International Semiconductor Road Map, it will become possible to integrate approximately a billion transistors on a single chip by 2009. The implication of this is that we will be able to integrate hundreds of processor sized cores in a System on Chip. This huge capacity offers a lot of opportunities for designers and electronic industry. It also offers challenge to researchers in the area of SoC architectures to come up with high performance scalable architectures which not only allow reuse of IP cores but also the reuse of interconnection infrastructure. Over the last few years many research groups in the world have proposed packet switched networks for on-chip communication among cores on SoC. This new way of SoC design is called Networks on Chip (NoC).

In this tutorial we will start with discussing the evolution of the NoC concept. The NoC paradigm borrows and adapts a lot of concepts from the area of Computer Networks and Distributed Systems. We will review these concepts in the context of SoC design. A few representative NoC architectural proposals from different research groups will be described to highlight important architectural issues. NoC paradigm will only be used by industry if new CAD tools become available for evaluation of possible alternatives and for mapping applications to available NoC architectures. We will describe a few of the important attempts in this direction.

In the end, we will discuss limitations of current proposals and present a list of interesting research problems in the areas of NoC architectures and tools for NoC design.

Z. Pliva
BIST in SOC

Abstract

The lecture is focused on the problem of IC testability improvement. The diagnostic access standards IEEE 1149.1-6 and the prepared standard IEEE 1500 form a basis on which an IC diagnostic subsystem can be built. In the lecture we describe different Test Access Mechanisms (TAM). We discuss effectiveness of the scan chain diagnostic access methods; Boundary Scan based methods and Random Access Scan methods. One of the important features of the TAM is the power consumption during test. It can be relatively high for shifting test patterns through long chains. We discuss the possibilities of power consumption reduction of the scan chained diagnostic access methods and of the Random Access Scan techniques. The diagnostic access scan techniques form a platform for Built-In Self Test Equipment design. Based on the diagnostic access standards, different autonomous pattern generators and test response compaction methods can be designed. We explain the published BIST solutions and compare the diagnostic hardware overhead, test data reduction and test time. Several methods of test pattern generation can be used in BIST. Finite automata like Linear Feedback Shift Registers and Cellular Automata are often used as automata that generate and decompress test patterns and that create and store the IC output response signature. The most effective are those that use weighted random test patterns. As the weighed random testing cannot overcome the problem of hard-to-test faults, mixed-mode test approaches are commonly adopted. In these approaches deterministic testing is mixed with pseudo-random or weighted-random testing. We compare these methods and give recommendation how to use them effectively. For designs with dissipated energy and test time restrictions the autonomously generated test patterns are not suitable and deterministic test patterns are used. We discuss the methods of deterministic test pattern compression and decompression and we compare the hardware overhead, amount of stored data and the time for test.

Abstract

In this tutorial lecture, a methodology for probabilistic modeling of physical defects in CMOS gates and estimation of the effectiveness of test patterns for detecting physical defects will be discussed. Quality of testing depends also on quality of test patterns generated for a circuit under test. Evaluation criteria for digital circuits testing are fault coverage and test application time. Low efficiency of the classical stuck-at fault model in real defect coverage in CMOS logic has initiated the need of new test approaches. These approaches extend the CMOS standard cells characterization methodology for voltage defect based testing and for I_DDQ testing. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. For shorts at the inputs two types of cell simulation conditions – “Wired-AND” and “Wired-OR” – are used. Examples of industrial standard cells characterization indicate that a single logic fault probability table is not sufficient. Separate tables for “Wired-AND” and “Wired-OR” conditions at the inputs are needed for full characterization and hierarchical test generation.

V. Stopjakova
Current-based Test Methods for Digital and Mixed-signal Circuits

Abstract

The advanced trends in recent VLSI circuits production lead towards extremely complex systems that include digital and analog parts, memory architectures, and other embedded blocks on a single chip. The mixed-systems realized in deep sub-micron technologies bring also an emergence of testing that becomes of the utmost importance in order to provide the required quality of production. Since the conventional voltage test strategy is not effective in covering hard-detectable physical defects occurring in recent technologies, other test techniques such as current-based strategies might be used to augment the classical approaches. Examples of built-in current monitors for both static supply current (I_DDQ) as well as transient supply current (I_DDT) measurement are presented. Although current test techniques are very efficient in detecting a wide class of defects these methods suffer from poor versatility and their use in deep sub-micron technologies is limited. Therefore, a new alternative strategy for classification of defective circuits based on analysis of the circuit’s current response using artificial neural networks is described and the experimental results achieved are presented.

Abstract

With increasing system complexities and higher operational frequencies, timing is becoming a very important aspect of a complex digital circuit design. The higher clock rate, shrinking geometry, increasing metal density, etc. are resulted in defects that cause speed faults. Therefore for complex high speed VLSI circuits and systems, delay testing is necessary to reach an acceptable quality level. The stuck-at fault model does not cover speed-related defects very well. Until now, some delay fault models have been investigated and published – path delay, gate delay, segment delay and transition faults. Some algorithms have been developed for generating robust or non-robust test set for delay faults. The lecture will cover basic concepts of delay testing, delay fault models, tests and test generation techniques for delay faults.

Abstract

Electrical test means Functional Test (FT), In Circuit Test (ICT) or Boundary Scan Test (BST) or even a combination of these technologies. However, with modern technology, like SMD (Surface Mounted Devices) technology, BGA (Ball Grid Array) components and extremely small component dimensions, electrical test alone does not meet the quality requierments.

Electrical test can not identify bad soldering and bad alignment of  components, as examples. Missing decoupling capacitors and so on can not be detected because of it is hard to get physical access for testprobes. Do not forget that digital designs contains a lot of analogue devices!

The tutorial will discuss today test technology with equipment for ICT and BST as well as its pros and cons. And as the addition of this, Inspection. Inspection has traditonally been performed manually but this is not realistic today with board crowded by components. Today Inspection is performed by machine vision. Optical technique named Automated Optical Inspection (AOI) and more advanced X-ray inspection (AXI). AOI and AXI is not the future, it is here today.

Abstract

Testing of analogue circuits is more complex and expansive process in comparison with testing the digital circuits. In many respects it is defined by such features of the analogue circuits as non-linear and continuos character of the input signal transformation, complex functional dependence between input and output signals, high sensitivity of output parameters to variations of in-circuit and external parameters, etc. Well known, there are no universal formalistic approaches nowadays. The methods of analogue circuits testing offered and realised to the present time carry the local character and are used at a level of the partial specific applications. The approach of design-for-testability (DFT) of analogue electronic devices is the most effective and promising solution. DFT approach allows at early stages of the device development to carry out a choice of conditions for the future testing, formation of the tests and estimation of both their completeness and efficiency. In the lecture the different design-for-test approaches, techniques and methods of electronic devices will be considered. Special attention is addressed to architecture, implementation and use of the mixed-signal test bus.