Tutorials on Analog and Digital Test

Tutorials on Analog and Digital Test

Monday, October 7, 2002. 12:00 am – 6:00 pm

TUTORIAL 1: Design for Test of Systems on Chip: Analog Test

Presenters: V. Stopjakova , V. Mosin, M. Blyzniuk

The tutorial is focused on the overview of on-chip test strategies for complex mixed-signal systems, methods of testing analog circuits, and methods of defect analysis in VLSI circuits. The advanced trends in recent VLSI circuits production lead towards extremely complex systems on chip that include both digital and analog parts, and memory architectures. Testing has to keep pace with circuits design development to provide the required quality of production. Adaptive multi-parametric test methods able to handle defect detection in SoC realised in deep sub-micron technologies might be a solution. The place of testing in the life-cycle of electronic devices, complexity and cost issues, the features of faults in analog circuits, testability of analog circuits, testing and fault diagnosis, functional and structural testing, hierarchical test approaches, built-in self-test in analog circuits, methodology for probabilistic modelling of physical defects in CMOS gates and estimation of the effectiveness of test patterns for detecting physical defects will be discussed.

Wednesday, October 9, 2002. 9:00 am – 6:00 pm

TUTORIAL 2: Design for Test of Systems on Chip: Digital Test

Presenters: J. Hlavicka, V. Drabek, O. Novak, Z. Pliva, Z. Kotasek, E. Gramatova

The tutorial is focused on diagnostic methods and design for testability of integrated circuits. An overview of nowadays design for testability tools and the problems of testability will be presented. A classification and short description of bioinspired methods (phylogenetic, ontogenetic and epigenetic principles) applied for design of fault tolerant reconfigurable systems in recent years will be discussed. Different methods of built-in self-test methods and a short overview of the theory of partial scan for built-in test will be given. Low efficiency of the classical stuck_at fault model in real defect coverage in MOS logic has initiated the need of new test approaches. Defect classification, taxonomy of fault models, and advanced test pattern generation algorithms will be presented as a perspective basis for achieving high defect coverage in digital circuits.

The tutorials are organized in the frame of the EC Project REASON.

Contact and registration: raiub@pld.ttu.ee, artur@pld.ttu.ee

TUTORIAL 1:	Design for Test of Systems on Chip: Analog Test
	Presenters: V. Stopjakova , V. Mosin, M. Blyzniuk
	The tutorial is focused on the overview of on-chip test strategies for complex mixed-signal systems, methods of testing analog circuits, and methods of defect analysis in VLSI circuits. The advanced trends in recent VLSI circuits production lead towards extremely complex systems on chip that include both digital and analog parts, and memory architectures. Testing has to keep pace with circuits design development to provide the required quality of production. Adaptive multi-parametric test methods able to handle defect detection in SoC realised in deep sub-micron technologies might be a solution. The place of testing in the life-cycle of electronic devices, complexity and cost issues, the features of faults in analog circuits, testability of analog circuits, testing and fault diagnosis, functional and structural testing, hierarchical test approaches, built-in self-test in analog circuits, methodology for probabilistic modelling of physical defects in CMOS gates and estimation of the effectiveness of test patterns for detecting physical defects will be discussed.

TUTORIAL 2:	Design for Test of Systems on Chip: Digital Test
	Presenters: J. Hlavicka, V. Drabek, O. Novak, Z. Pliva, Z. Kotasek, E. Gramatova
	The tutorial is focused on diagnostic methods and design for testability of integrated circuits. An overview of nowadays design for testability tools and the problems of testability will be presented. A classification and short description of bioinspired methods (phylogenetic, ontogenetic and epigenetic principles) applied for design of fault tolerant reconfigurable systems in recent years will be discussed. Different methods of built-in self-test methods and a short overview of the theory of partial scan for built-in test will be given. Low efficiency of the classical stuck_at fault model in real defect coverage in MOS logic has initiated the need of new test approaches. Defect classification, taxonomy of fault models, and advanced test pattern generation algorithms will be presented as a perspective basis for achieving high defect coverage in digital circuits.